Limits. Symbol. Parameter. Conditions. −40°C. +25°C. +85°C. Units. Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. IL. Quiescent Device. VDD = V. Data sheet acquired from Harris Semiconductor. SCHSC – Revised September The CDUB types are supplied in lead hermetic dual-in- line. Order Number CD C National Semiconductor Corporation . This datasheet has been downloaded from: Datasheets for.
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Each pair shares a common gate pins 6,3, You can also document mistakes or missteps that occurred, e. Output of cd datasheet inverter. Remember to ground the AI- terminals. Application of Ddatasheet logic. For example, consider 22,5,7 ; 1,3, Describe the differences between the screenshots other than that they are inverted. It should look as shown in Figure 8.
Enter search terms or a module, class or function name. Quick search Enter search terms or a module, class or function name. Attach screen shots for different Cd datasheet. Each pair shares a common gate pins 6,3, Therefore, this circuit is an oscillator. Attach screen shots for different VDD. If you only give a logic diagram, dztasheet pin numbers between logic elements. Thank you for keeping our lab clean and organized.
Connect pin 9, which serves as D input of the latch to DIO0. Show 3 screen shots of inverter outputs. Can you tell what it does?
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Estimate Vtp from Ids-Vgs curves. For the complete circuit you will need 4 CD chips. In summary, the output of the inverters will oscillate between 0 and Vdd. You are encouraged to write down your experience with this lab along with any feedback or suggestions. The other two pairs are daasheet general purpose. Consider the circuit shown in figure Measure the Ids-Vds curves for a multiple Vgs values. Capture a screen shot.
What to do in the lab report Datasbeet screen shots for working frequencies, and for too high frequencies such that transitions between 0 and VDD are not complete. Schematic of D flip flop. At what input voltage does the output transition to logic low?
Set the function generator to output a Hz sine wave, 5vpp, 2. The pin diagram seen in figure 2 shows the package layout and various pin connections for ALD Construct 3 inverters using a CD by making the following connections: There are 6 parts and a bonus. Created using Sphinx 1.
Remember to ground the CH – terminals. Measure the output voltage of the second inverter and the voltage across the capacitor with the scope.
It should look as shown below in Figure 5. This is the opaque phase of the latch. A steady low should appear inspite of changing D to logic High since the previous value at D-input was low.
Quick search Enter search terms or a module, class or function name. You do not have to draw a gate level schematic if you can determine the logic function implemented. Compare measured Vdsat with 1st order theory, i. Clean up Previous datashset 7. Build a chain of 3 inverters by connecting your inverters in the order shown in figure 4. Have your GTA sign cd datasheet on each part before proceeding to the next part.
Therefore, this circuit is an oscillator. The output of the first inverter will be Vdd and the output of the second inverter will be zero. Find the Vds at which the drain current saturates, defined as Vdsat, for all Vgs measured from the Ids-Vds curves. The two inverters can be built from a CD by making the following connections: During the transparent phase of the latch, i.
The other two pairs are more general purpose. If you only give a logic diagram, show pin numbers between logic elements. Enter search terms or a module, class or function name. Describe the differences between the screenshots other than that they are inverted. Proceed as shown in Figure 6.