LXTALE from Intel Corporation. Find the PDF Datasheet, Specifications and Distributor Information. (This Datasheet also supports the LXT PHY.) Applications. Product Features LXTALE – Extended (° to 85 °C amb.) ▫ LXTALC. LXTALE Networking & Communications – Ethernet Products – Ethernet PHYs/ Macs/transceivers Details, datasheet, quote on part number: LXTALE.

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August 7, 83 LXTA 3. August 7, 51 LXTA 3. August 7, 87 LXTA 3. Valid instructions are listed in Table Not guaranteed or production tested.

LXTALE datasheet(39/90 Pages) INTEL | V Dual-Speed Fast Ethernet PHY Transceiver

This function can be disabled by setting Register bit If link pulses or data are not received by the maximum receive time-out period msthe polarity state is reset to a non-inverted state. The signal detect pin on a 5 V fiber transceiver interface should use the logic translator circuitry as shown in Figure See Figure 35 on page 67 for SQE timing parameters.

Nine signals are used to pass received data to the MAC: Test loopback in this mode is enabled by setting Register bit 0. August 7, 69 LXTA 3. The fiber interface operates at Mbps and does not support 10FL applications. August 7, Datasheet Datasheet Document: Parameter is guaranteed by design; not subject to production testing.


The reset bit should be polled to see when the part has completed reset 0. When an event such as receiving a packet occurs it is edge detected and it starts the stretch timer. The LXTA also provides two dedicated interrupt registers. Test data driven with respect to the falling edge of TCK.

Configuration control of autonegotiation, speed, and duplex mode selection is handled differently for each. Figure 25 shows a typical example of an LXTA-to When the Link Integrity Test function is enabled the normal configurationit monitors the connection for link pulses. Default values of Register bits 4. This interface operates at either 10 Mbps or Mbps. As a matter of good practice, these supplies should be as clean as possible.

The LED drivers can operate as either open-drain or open-source circuits as shown in Figure 8. Scrambler bypass is provided for diagnostic and test support. TDO does not have an internal pull-up or pull-down. Before committing to a specific component, contact the manufacturer for current product specifications and validate the magnetics for the specific application.

LXTALE Datasheet PDF – Intel

August 7, 43 LXTA 3. Once link pulses are detected, data transmission is enabled and remains enabled as long as either the link pulses or data transmission continue.

The connection of a clock source to the XI pin requires the XO pin to be left open. The receiver automatically decodes the polynomial whenever IDLE symbols are received.

Link failure causes the LXTA to re-negotiate if auto-negotiation is enabled. The LXTA may contain design defects or errors known as errata which may cause the product to deviate from published specifications.


It includes a state machine, data register array, and instruction register. RO hex 1. Tie High for FX mode Register bit Auto-Negotiation Expansion Address 6 Bit 6. Added Lx9t71ale values to Vcc current.

LXT971ALE Datasheet

This bit is only valid when auto negotiate is enabled, and is equivalent to Register bit 1. The following paragraphs discuss LXTA operation from the reference model point of view. When not transmitting data, the LXTA generates Each burst consists of up to 33 link pulses spaced datashheet Status Register 2 Address 17 Bit Interrupt is cleared by reading Register If another event occurs before the stretch timer expires then the stretch timer is reset and the stretch time is extended.

If this condition occurs, the LXTA returns to the auto-negotiation phase if autonegotiation is enabled. On the transmit lxt971lae, the LXTA has an active internal termination and does not require external termination resistors.

Normally, Register bit 6. The FEFI consists of 84 consecutive ones followed by a single zero. Center-tap current may be supplied from 3. Values are relative approximations.